VHDL MC68881 – Complete

• 

  MattP

  7 mars 2026 à 9h51 #391830

  Just to make you aware that I have finished a complete VHDL08 recreation of the 68881 processor including CIR and peripheral interfaces. Please feel free to use as you see fit. It needs speed optimisations but has *all* ops of the physical chip.

  Full instruction set: FADD, FSUB, FMUL, FDIV, FSQRT, FMOD, FREM, FSCALE, FSGLDIV, FSGLMUL, FABS, FNEG, FINT, FINTRZ, FGETEXP, FGETMAN, FTST, FCMP.
  Transcendental engine: FSIN, FCOS, FTAN, FSINCOS, FASIN, FACOS, FATAN, FATANH, FSINH, FCOSH, FTANH, FETOX, FETOXM1, FTWOTOX, FTENTOX, FLOGN, FLOGNP1, FLOG2, FLOG10. BRAM-based seed tables with Taylor/CORDIC iteration.
  Data movement: FMOVE (all formats including packed decimal .P), FMOVEM (register lists and control registers), FMOVECR (ROM constants).
  Program control: FScc, FBcc, FDBcc, FTRAPcc, FNOP with BSUN trap gating.
  System control: FSAVE/FRESTORE with Null/Idle/Busy frame support (45-word Busy frame with full sub-unit save/restore hierarchy).
  IEEE 754 compliance: NaN propagation (SNaN/QNaN discrimination, payload preservation), infinity handling, signed zero, gradual underflow, all four rounding modes (nearest, zero, +inf, -inf), single/double/extended precision.
  Exception handling: Per-operation FPSR exception policies, FPCR trap enable, accrued exception accumulation.
  Peripheral interface: Register-mapped bus interface with DSACK handshake, suitable for M68000/M68010 peripheral-mode operation.
  CIR coprocessor interface with FSAVE/FRESTORE Busy frame support and full exception dialog paths

  https://github.com/mattuna15/68881-fpga